The present disclosure relates to semiconductor devices, and specifically, to a semiconductor device having a chip on chip (CoC) structure.
As technologies for fabricating semiconductor devices continue to progress in miniaturization, the number of transistors constituting a large-scale integration circuit (LSI) continues to increase. Moreover, as components, in particular, systems of the LSI become complex and increase in scale, memory capacity required by a system LSI may possibly increase, and thus, for the system LSI on which a large-scale memory is mounted, there is a need for a highly efficient mounting method.
On the other hand, as a method for connecting the LSI and a package, a wire bonding method and a flip chip method have been widely used. When the wire bonding method or the flip chip method is used in mounting memory devices, the memory devices have to be mounted in a chip of the system LSI, on a chip mounting substrate, or on a mounting substrate. This results in limitation on mount capacity, an increase in mounting area on the substrate, an increase in mounting cost, or the like. To solve the problem, a CoC structure has been used.
As illustrated in FIG. 10, a semiconductor device 900 having a common CoC structure includes an upper semiconductor chip 901 and a lower semiconductor chip 902 each having a circuit formation surface and a plurality of pads (not shown) on the circuit formation surface. The upper semiconductor chip 901 and the lower semiconductor chip 902 are disposed so that their circuit formation surfaces face each other, and are electrically connected to each other via a plurality of bumps 904 disposed on the plurality of pads. A region between the upper semiconductor chip 901 and the lower semiconductor chip 902 is filled with an underfill resin 905. The lower semiconductor chip 902 has pads for wire bonding (not shown) which are provided outside a region in which the semiconductor chip 902 is mounted, and the lower semiconductor chip 902 is electrically connected to the substrate 903 via wires 906. The semiconductor chips 901 and 902 and the wires 906 are entirely covered with a molding resin 907.
With the CoC structure, the plurality of semiconductor chips 901 and 902 can be mounted on the substrate 903, so that chips can be connected to each other with space between the chips being saved compared to the commonly used wire bonding method and the flip chip method.
Incidentally, in the case of the CoC structure illustrated in FIG. 10, power is supplied to the upper semiconductor chip 901 via the lower semiconductor chip 902, which causes a problem where a voltage drop (IR drop) occurs due to an insufficient power supply voltage to the upper semiconductor chip 901. Moreover, since the lower semiconductor chip 902 is covered with the upper semiconductor chip 901, power cannot be supplied from above directly to a center section of the lower semiconductor chip 902. Therefore, a voltage drop also occurs in supplying power to the center section of the lower semiconductor chip 902. That is, the influence of the voltage drop varies the working speed of the transistors of the LSI, which affects the operation timing of the LSI unless the influence the voltage drop is taken into consideration. This may result in malfunctions of the LSI and severe problems relating to the yield, etc.
To solve the above-discussed problems, Japanese Unexamined Patent Publication No. 2008-159607 describes a semiconductor device having a CoC structure, wherein positions of a plurality of semiconductor chips stacked on an interconnect substrate are shifted from each other so that power is supplied from the substrate directly to upper ones of the semiconductor chips.
Japanese Unexamined Patent Publication No. 2011-119609 describes a semiconductor device including a substrate and a conductive pattern formed as a dam on a principal surface of the substrate to solve a problem where an underfill flows and extends in flip-chip mounting, wherein power supply capacitance is generated by the formed conductive pattern to stabilize power to chips.
Japanese Unexamined Patent Publication No. 2010-141080 describes a semiconductor device having a CoC structure, wherein a semiconductor logic circuit chip smaller than a semiconductor memory chip is stacked on the semiconductor memory chip to reduce the size of the semiconductor device.